Microelectronic packages and package assemblies are now commonly produced to include multiple interconnected devices. Advancements in microelectronic packaging have brought about significant improvements in package functionality, device density, and package size. Nonetheless, still further improvements in these key areas continue to be sought. Microelectronic packages containing multiple interconnected devices embedded in a single molded body (referred to herein as “System-in-Packages” or, more simply, “SiPs”) can be produced with high device densities and relatively compact footprints. This is particularly true when the SiP is produced to have a three dimensional (3D) package architecture; that is, to contain multiple levels or layers of devices, which overlap as taken along an axis extending parallel to the package centerline.
SiPs are, however, associated with certain limitations. For example, SiPs can suffer from relatively high heat concentrations and poor thermal dissipation, which can reduce the functionality of semiconductor die within the SiP. If this is overly problematic, an alternative 3D package architecture can be chosen. For example, a so-called “Package-on-Package” or “PoP” configuration can be utilized wherein a first microelectronic package is stacked on a second microelectronic package and interconnected therewith. Relative to 3D SiPs, PoP assemblies often provide improved heat dissipation with a corresponding penalty in device density. Design rules and conventional practices for producing PoP assemblies can, however, limit the options available for interconnecting the stacked packages, which, in turn, can place undesired restrictions on the functionality of the PoP assembly.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the subsequent Detailed Description. It should further be understood that features or elements appearing in the accompanying figures are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of certain elements or regions in the figures may be exaggerated relative to other elements or regions to improve understanding of embodiments of the invention.